1. Technical Field of the Invention
The present invention relates to a semiconductor memory device capable of changing access timings after completion of a semiconductor chip.
2. Prior Art
A semiconductor memory device is produced in the form of a semiconductor LSI and comprises an array of memory cells and an internal control circuit. The memory cell array stores data. The control circuit writes data to each memory cell or reads data from each memory cell in the memory cell array. Generally, a delay circuit is integrated in the memory LSI in the form of a gate delay to control or adjust access timing of the memory cell array. Basically, a semiconductor memory device designer adjusts the number of gate stages to optimize access timing by means of simulation using device parameters.
Patent document 1 describes the memory design technology capable of setting desired delay times in accordance with memory cell array configurations and capacities. Further, patent documents 2 and 3 also describe the similar technologies.
Patent document 1 is Japanese Patent Unexamined Publication No. Hei. 08-123838. Patent document 2 is Japanese Patent Unexamined Publication No. 2002-25255, and Patent document 3 is Japanese Patent Unexamined Publication No. 2002-216481.
When the most recently developed process is used or chip dimensions are reduced, however, a large difference occurs between a simulation result and actual chip characteristics, often causing an access error of the memory array due to improper setting of the delay stages. In such case, the chips having the access error must be assumed to be rejected. On the other hand, some delay circuits are capable of physically changing the number of delay stages. The method of changing the number of delay stages is performed by dissolving a resin covering the LSI with chemicals and the like to expose the surface of LSI, and then directly cutting and pasting metal wires by using FIB (Focused Ion Beam) or other apparatuses. Accordingly, this method is not practical and only usable for error analysis. The defective chips cannot be saved as acceptable products according to such a method.